In the processing of a substrate in a chamber to fabricate circuits and displays, the substrate is typically exposed to energized gases that are capable of, for example, depositing or etching material on the substrate. For example, in a chemical vapor deposition (CVD) process, process gases are energized by for example, microwave or RF energy, to deposit a film on the substrate. The deposited films are further processed to create devices on the substrate such as, for example, metal-oxide-semiconductor field effect transistors (MOSFETs), which typically have a source region, a drain region, and a channel region there between. A gate electrode, above and separated from the channel by a gate dielectric, controls conduction between the source and drain. The performance of such MOSFETs can be improved, by for example, reducing supply voltage, gate dielectric thickness or channel length. However, these methods have diminishing returns as transistors shrink in size. For example, the advantages of reducing channel length, such as increasing the number of transistors per unit area and increasing the transistor saturation current, begin at very small channel lengths to be offset by carrier velocity saturation effects. Benefits from gate dielectric thickness reduction, such as decreased gate delay, are offset by increased gate leakage current and charge tunneling through the dielectric which may damage the transistor over time. Reducing the supply voltage allows for lower operating power, but reductions in the supply voltage are limited by the transistor threshold voltage.
Strain engineering, in which the atomic lattice of a deposited material is strained to affect the properties of the material, is used to further enhance transistor performance. Lattice strain can increase the carrier mobility of semiconductors, such as for example silicon, which increases the saturation current of transistors, thus increasing their performance. Strain can be introduced into materials formed on substrates in a number of ways. For example, localized strain and stress can be induced in the channel region of the transistor by the deposition of component layers of the transistor which have internal compressive or tensile stress. In one version, silicon nitride layers are used as etch stop layers and as spacers during the formation of silicide layers on the gate electrode, and can be deposited to have a tensile stress which can induce a stress in the channel region. Examples of embodiments of layered structures capable of inducing strain in the channel region are described, for example, in “Process-Strained SI (PSS) CMOS Technology Featuring 3D Strain Engineering,” Ge et al, IEEE 0-7803-7873-3/2003, which is herein incorporated by reference in its entirety. However, such stressed layers may still fail to provide sufficient carrier mobility improvement to meet the rapidly advancing transistor performance requirements.
In yet another method, the lattice structure of the channel region can be strained by forming structures comprising silicon germanium on the substrate. Strain engineering with these materials centers on the nearly 4.2% lattice mismatch between single crystal Ge and Si lattice structures. The electronic conduction and valence band structure of SiGe was well established following the early preparation of homogeneous SiGe alloys nearly four decease ago. The advent of pseudomorphic deposition of Si on GexSi1-x extended this understanding to strained lattice structures and enabled examination of electrical characteristics of Si. The strained silicon typically has higher carrier mobility compared to the relaxed Si lattice structure, which is at least partly due to reduced inter-valley phonon scattering and lower effective mass. An example of strained Si formed over silicon germanium is described, for example in “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET'S”, Rim et al, IEEE Transactions on Electron Devices, Vol. 47, No. 7, July 2000, which is herein incorporated by reference in its entirety.
The use of silicon germanium as a source and drain material to induce strain in a neighboring channel region has also been explored, for example in “A Logic Nanotechnology Featuring Strained-Silicon,” Thompson et al, IEEE Electron Device Letters, Vol. 25, No. 4, April 2004, and “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS,” Chidambaram et al, IEEE 2004 Symposium on VLSI Technology, Digest of Technical Papers, both of which are herein incorporated by reference in their entireties. However, the silicon germanium material has not provided sufficient carrier mobility improvement to allow for the development of next generation devices with the desired performance.
Thus, there is a need for semiconductor devices having transistors with improved carrier mobility that provide enhanced device performance, and methods of fabricating such transistors. There is a further need for materials capable of inducing strain in channel regions of transistors to provide a desired level of carrier mobility and change conductance in the channel.